1. Field of the Invention
The present invention relates to a programmable logic device, and more particularly to a latching sense amplifier for a programmable logic device.
2. Description of the Related Art
Referring to FIG. 1, programmable logic devices (PLDs) typically use one or more interconnect arrays 10 that are programmed via a plurality of memory cells 12 (e.g. EPROM, EEPROM, flash EPROM, or flash EEPROM cells) to make various interconnections within the PLD that are specific to a desired design. In interconnect array 10, the control gate of a memory cell 12 is connected to a wordline 14, the drain of the cell is connected to a bitline 16, and the source of the cell is connected to ground or virtual ground.
An erased memory cell (i.e. a cell having a low threshold voltage Vt) becomes conductive if a high voltage Vcc is provided on its control gate, thereby effectively creating a connection in the array. In contrast, a programmed cell (i.e. a cell with a threshold voltage Vt above Vcc) does not become conductive if a high voltage is provided on its control gate. Thus, a programmed cell is not capable of affecting the state of bitline 16, and does not constitute an array connection.
Typically, a sense amplifier 18 is used on each bitline 16 of array 10 to sense and amplify the change of voltage on bitline 16, which may only vary by tens of millivolts, thereby achieving full logic levels at the array output line PT. Because sense amplifiers are typically in speed critical paths, sense amplifiers having very small switching delays are desirable. FIG. 2 illustrates one embodiment of sense amplifier 18.
Sense amplifier 18 is powered up or enabled by applying a logic 0 signal to line ENA, thereby turning off N-channel transistor 22, and a logic 1 signal to line ENA. Thus, the voltage level on a feedback line FB is established by a weak pull-up N-channel transistor 20 which is turned on by the logic 1 signal provided on line ENA and a strong pull-down N-channel transistor 21 which is controlled by the signal on bitline 16. The voltage provided to feedback line FB controls the state of N-channel transistor 24, which operates in its linear range.
A weak P-channel transistor 26 and the strong N-channel transistor 24 provides a low trigger point at a bitline voltage on the order of 0.75 volts. If the voltage on bitline 16 transitions high, transistor 21 turns more on, thereby pulling the voltage on feedback line FB lower. This lower voltage in turn causes transistor 24 to turn more off, thereby pulling up the voltage on bitline 16 less and assisting the next movement on bitline 16 (i.e. the voltage going low). Conversely, if the voltage on bitline 16 transitions low, the voltage on feedback line FB is higher. This higher voltage in turn causes transistor 24 to turn more on, thereby pulling bitline 16 to a higher voltage (via transistor 26 which serves as a current source, and operates in saturation mode).
Thus, the voltage on line ABL is controlled by transistor 24 in conjunction with bitline 16. In response to the signal on bitline 16, ratioed inverters 27 and 28 ensure that the output voltage provided on output line PT is at CMOS levels. Table 1 shows one example of logic 0 and logic 1 voltage values on the lines 16, FB, ABL, NBL, and PT.
TABLE 1 ______________________________________ Signal Logic 1 Logic 0 Difference ______________________________________ 16 0.769 v 0.746 v 0.023 v FB 1.77-1.88 v N/A N/A ABL 2.76 v 2.18 v 0.58 v NBL 0.491 v 3.33 v 2.84 v PT 4.4 v 0 v 4.4 v ______________________________________
Table 1 shows that a small swing in the voltage on bitline 16 can produce a switch in the CMOS signal on output line PT.
Depending upon the state of EPROM 12 as controlled by word line 14, the voltage on bitline 16 is pulled lower or higher to indicate a logic 0 or logic 1 signal. If the signal on word line 14 is a logic 1 and assuming that EPROM 12 is erased, then the voltage on bitline 16 is pulled lower to indicate a logic 0 signal. When biased on, EPROM 12 pulls the voltage on bitline toward virtual ground VG. As shown in FIG. 2, virtual ground VG is separated from actual ground by transistor 25, which is controlled by a signal on line ABL.
Sense amplifier 18, however burns power constantly, irrespective of the voltage on bitline 16. Specifically, transistor 24 is always at least minimally on, thereby providing a current branch through conducting transistor 26, transistor 24, and transistor 23 (or additionally transistor 25 if EPROM 12 is on). Note that because of the analog signal levels provided on lines ABL and NBL, the transistors (not shown) which form inverters 27 and 28 also form current paths.
Thus, prior art sense amplifier 18 typically draws substantial amounts of DC current (on the order of a few hundred microamps) in both the bitline high and bitline low states, in addition to the large AC switching current generated during a transition in bitline state. In fact, sense amplifiers are generally responsible for drawing the majority of the DC current in a PLD. This large current draw is an undesirable side effect of high speed sense amplifiers.
Approximately 25% to 50% of the sense amplifiers in a PLD are not used in a typical user design, even when a large percentage of other resources in the device are used in the design. It would be desirable to completely shut off these unused sense amplifiers, thereby reducing the overall DC current drawn by the PLD. However, a PLD typically has hundreds of sense amplifiers. Therefore, generating the necessary information and control logic required to determine which sense amplifiers are on and off significantly increases the overhead involved in the control logic and the associated routing of control lines across the device.
Another known method to reduce the amount of power consumed by a PLD includes fitting the desired design into a minimum number of blocks within the PLD, thereby allowing unused blocks of sense amplifiers to be entirely shut down by driving the ENA signal for those blocks low. Unfortunately, this method is only effective when the desired design does not use a majority of the other logic resources in the PLD. This approach also restricts the user's flexibility in programming the PLD for a desired application, for example with regard to device pinout location.
Yet another known method to reduce the amount of power consumed by a PLD includes designing the sense amplifier such that a bitline high state consumes less power than a bitline low state. Thus, for a bitline having no connections in the design, i.e. a bitline on which all of the memory cells are programmed, the sense amplifier is always in a lower power consumption, bitline high state. This method of power control is unsatisfactory because the unused sense amplifiers nonetheless remain powered up and, therefore, still draw significant DC current.
Thus, a need arises for a sense amplifier which reduces the DC current drawn by the PLD without significantly increasing overhead and restricting the programmability of the device.